CPU Architecture Deep Dive: What’s Under the Hood?

14 Tem 14:18

big.LITTLE is architecturally deeper than just slapping “small slow core + big fast core” on the same die. The trick is the **Core-Core interconnect** (ARM calls it CCI, AMD calls it Infinity Fabric in variants), which lets the scheduler move threads between efficiency and performance cores in <100ns without flushing L1/L2. That’s why you see SoCs like Apple M3 kicking both Cortex-X4 and Cortex-A720 at the same time—it’s a **heterogeneous scheduler run-time**, not a static partition. Real-world latency numbers from AnandTech’s M3 teardown show big→LITTLE migration can actually be slower *if* the data working set is >2 MB, because you evict the L2 entirely. ARM’s “regular big cores” (Cortex-X4, Neoverse V2) now run a **wider front-end** (8-wide decode vs older 6-wide) but the real IPC uplift comes from **predictor upgrades**: the Branch Target Buffer (BTB) is now 9k entries with 16-cycle mispredict penalty versus 4k/20-cycle in Cortex-X1. Compiler optimizations? They’re only half the story—those wider decoders saturate the **decode→rename pipeline** if the compiler doesn’t chunk loops into basic blocks smaller than 25 instructions; GCC 13’s -funroll-loops-innermost now defaults to 16 to avoid front-end stalls in crypto workloads. Check Apple’s latest LLVM patches for A17 Pro—there’s a new `-mbranch-hint` that **dynamically merges** static branch hints with the new 1MB ITT (Indirect Target Table), cutting mispredicts on SwiftUI’s control flow by ~12 % in iOS 17 benchmarks. As for pipelining, Intel’s Arrow Lake leakage graphs show a typical 14-stage pipeline only adds ~3 % IPC versus 10 stages when you count branch penalties; the big win is the **backend** shift—LSD (Loop Stream Detector) now handles 7-entry loops versus 3-entry in Alder Lake, so the compiler can keep more loops in the LSD buffer without flushing the pipeline every iteration.